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- 斋米
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- 斋豆
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- 2010-10-7
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- 1970-1-1
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Intern positions:
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ASIC Design/Verification Intern (Vacancy:3) w8 H `' L1 z, C# ?: V2 |
Job Description:5 u# b4 T% U$ G' P- z" w: z
1. Design/Verification of video surveillance and audio & voice processor with integrated CODEC and amplifier
$ p; S( ]. o7 r$ v9 E1 W1 t5 o9 `2. Unit level & system level testbench build up with SystemC or OVM/UVM
& Y" {* }* g0 e( L$ e3. Bus Functional Models & APIs development
. f7 h# D0 m) _4. Verification of AMBA-based DMA, DDR Memory Subsystem, and peripheral interfaces including PCIe, USB, SPI, BT656/BT1120, I2C, etc.
& W5 w: T% {+ N) t; m# e, {2 M5. High-quality verification with Code Coverage analysis and functional coverage analysis& }5 W8 e% N5 S0 i; F: }
6. Provide support to ATE/DFT and Validation
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Job requirement: # F) Z. F2 z5 G- x. K* f: Z
1. Majoring in Electrical Engineering, microelectronics or image/graphics processing is preferred
, m7 t' L1 c2 t( Y- x! @ u2 H2. Master C/C++ coding and verilog coding, systemC and SystemVerilog is preferred0 b/ r! @1 S) x: T3 G
3. Strong DSP background is highly desirable
6 _0 i* ?, @+ { }/ G+ U4 |4. Knowledge of video coding standard including H264 MPEG-4 is preferable.
2 b" j }: E; Q7 @0 O3 |. ~5. Knowledge of RTL design and verification
1 B$ N/ U. ~$ w$ r0 Y6. Knowledge of Perl and Tcl scripting
# ~+ a9 C: j I2 G8 B" H2 c7. Able to understand Verilog RTL code, debug simulation errors, identify and fix RTL/Environment issues& d0 d1 }& p, g8 T$ k" z/ d3 l+ e
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联系人:' i* Q' D; m8 j# c# W
卢先生8 i4 c& B' n* t9 K
邮箱:lush123@sina.com$ b2 W2 m( B0 A8 I W0 ?% v, T+ Z# T
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