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Conexant 成都公司实习招聘

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发表于 2012-2-29 19:56:45 | 显示全部楼层 |阅读模式
Conexant  chengdu7 Q- j9 i& {! S4 i# k$ y
公司要招聘如下岗位的实习生
0 H8 o$ v6 U+ Y' g: u4 a( b$ \3 xIntern positions:
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+ [; p1 T: N* s; C5 KASIC Design/Verification Intern (Vacancy:3)
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Job Description:6 N2 |8 E! F6 z
1. Design/Verification of video surveillance and audio & voice processor with integrated CODEC and amplifier1 L7 V( n8 g8 g8 `8 U& j7 ~' |
2. Unit level & system level testbench build up with SystemC or OVM/UVM
1 N, o8 `; U3 G3. Bus Functional Models & APIs development
% }# i9 z( f9 N3 ]9 z, h( x4. Verification of AMBA-based DMA, DDR Memory Subsystem, and peripheral interfaces including PCIe, USB, SPI, BT656/BT1120, I2C, etc.! Y# G, x1 k+ K, Y+ X
5. High-quality verification with Code Coverage analysis and functional coverage analysis
! a3 n! E; r( _$ {* e6. Provide support to ATE/DFT and Validation
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Job requirement: , u7 [3 |# p5 P# F0 e# W: E3 Z
1. Majoring in Electrical Engineering, microelectronics or image/graphics processing is preferred7 R6 d+ o0 L- O! q, e" v: `
2. Master C/C++ coding and verilog coding, systemC and SystemVerilog is preferred
  Z* R* Q, B0 b3 k5 k( A8 e3. Strong DSP background is highly desirable
/ x3 |( _) V1 a) q2 u, B7 [4. Knowledge of video coding standard including H264 MPEG-4 is preferable.! D: {2 j  b' w
5. Knowledge of RTL design and verification) ]! t' \0 a) m  P9 M1 g% y
6. Knowledge of Perl and Tcl scripting % d* F* s8 ^, `& Z: @9 i: r& P( T2 ^
7. Able to understand Verilog RTL code, debug simulation errors, identify and fix RTL/Environment issues. @9 g0 ^. |6 k: }) ^
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Job requirement:
% `% C9 q2 Z; J$ @. X8 t) r1. Majoring in Electrical Engineering, microelectronics or image/graphics processing is preferred
. v# h/ v# \% j2. Master matlab is preferred
  `8 H; e4 @+ u0 p8 \3. Master digital signal process
' J' s3 `+ l0 }0 G7 F& M& ?4. Master Runge-Kutta and math analysis
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联系人:
9 P, ?/ Q9 F- J' r卢先生
# R5 _/ ?# I+ D7 v( ?2 t3 W请投简历至 邮箱:lush123@sina.com
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可以2500/月以上
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发表于 2012-2-29 22:40:44 | 显示全部楼层
题目变了,内容没变,坐等飞飞
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