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- 5262
- 斋米
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- 斋豆
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- 2010-10-7
- 最后登录
- 1970-1-1
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Intern positions:
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, ~- K4 c6 ~' }- |7 O! u' eASIC Design/Verification Intern (Vacancy:3)
2 A1 V( \: \ MJob Description:
# t P: y- d8 S* X$ x! _6 f% r7 h1. Design/Verification of video surveillance and audio & voice processor with integrated CODEC and amplifier y5 t6 k: Z3 [6 A9 O5 I# }
2. Unit level & system level testbench build up with SystemC or OVM/UVM
( O8 F. i- T m- z' F& r3. Bus Functional Models & APIs development
$ s8 b6 e2 V1 r5 \3 v8 U1 ]* c4. Verification of AMBA-based DMA, DDR Memory Subsystem, and peripheral interfaces including PCIe, USB, SPI, BT656/BT1120, I2C, etc.
4 I6 ?' e( r' S8 n/ E5. High-quality verification with Code Coverage analysis and functional coverage analysis
6 d s. b- D n8 W1 l9 W6. Provide support to ATE/DFT and Validation
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Job requirement: " n2 N& w, M1 f5 a* e- U0 S
1. Majoring in Electrical Engineering, microelectronics or image/graphics processing is preferred4 B* D. H6 X2 w2 ^0 O/ R6 O
2. Master C/C++ coding and verilog coding, systemC and SystemVerilog is preferred
, M$ C( ?$ q( y g: |, J3. Strong DSP background is highly desirable
4 N6 Q: \5 X$ n- I3 N J9 R- i4. Knowledge of video coding standard including H264 MPEG-4 is preferable.% {% i7 f1 \' s6 j& b
5. Knowledge of RTL design and verification7 M$ z9 e: M) i1 L; h$ \' Q
6. Knowledge of Perl and Tcl scripting / ~# U3 G4 \, Z8 i; [- m5 R
7. Able to understand Verilog RTL code, debug simulation errors, identify and fix RTL/Environment issues
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联系人:
9 E) L0 M1 T" [- F& F, r卢先生& o: |; {- w" D1 ^) x
邮箱:lush123@sina.com; l4 D0 q' a2 a1 h* I& @$ L
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