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- 2010-10-7
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Intern positions:* |$ ?( j, w! q3 q Q% O0 X
% ~0 z3 `' W( @6 Q) c4 w. OASIC Design/Verification Intern (Vacancy:3)9 l" R) k$ e, v& D& B$ U
Job Description:
" k2 P3 C4 `: B1 K/ T1. Design/Verification of video surveillance and audio & voice processor with integrated CODEC and amplifier1 E) t! l1 t0 q8 W
2. Unit level & system level testbench build up with SystemC or OVM/UVM
& B* Y9 G- k) ]0 n' W( j6 @3. Bus Functional Models & APIs development
\2 i: x- L/ u1 @. Q4. Verification of AMBA-based DMA, DDR Memory Subsystem, and peripheral interfaces including PCIe, USB, SPI, BT656/BT1120, I2C, etc.
- C7 o) A+ ~: @" t8 \9 G5. High-quality verification with Code Coverage analysis and functional coverage analysis, p# Q% W. s- N
6. Provide support to ATE/DFT and Validation
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* D' M; r5 ?+ ^+ Y t+ BJob requirement:
) u. S" {, j, f8 \4 G1. Majoring in Electrical Engineering, microelectronics or image/graphics processing is preferred) n9 J2 A1 U9 h. D# B. t8 J* c
2. Master C/C++ coding and verilog coding, systemC and SystemVerilog is preferred" A+ l& b' z8 [3 X
3. Strong DSP background is highly desirable* J' f/ Q" y7 w
4. Knowledge of video coding standard including H264 MPEG-4 is preferable.
8 O8 Z- G( O" r/ s5. Knowledge of RTL design and verification
- ?: R4 O; ^" O7 m C- D6. Knowledge of Perl and Tcl scripting 2 W: D: w+ Y/ a& {; f
7. Able to understand Verilog RTL code, debug simulation errors, identify and fix RTL/Environment issues
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! h% ]; R) ~' h( @. x5 V联系人:
! b1 I8 G! |# j& x& Q9 c5 m卢先生
( I2 ?7 H/ y- y邮箱:lush123@sina.com" B0 M2 U1 V! X$ Z. P. t
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