Conexant 成都公司实习招聘

zl182005

Conexant  chengdu
2 C2 ^9 ^0 @  D) ]" |公司要招聘如下岗位的实习生
2 }2 {5 ^# Q% u8 k, s2 X/ R2 h- yIntern positions:
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3 X. F) r! E) ]ASIC Design/Verification Intern (Vacancy:3)
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5 H5 g( V9 O- y8 U) kJob Description:
$ h3 p4 k4 z4 _9 K) I7 v/ x! o1. Design/Verification of video surveillance and audio & voice processor with integrated CODEC and amplifier
2. Unit level & system level testbench build up with SystemC or OVM/UVM
/ i. C5 ^# V5 L# ?8 ?; F3. Bus Functional Models & APIs development
4. Verification of AMBA-based DMA, DDR Memory Subsystem, and peripheral interfaces including PCIe, USB, SPI, BT656/BT1120, I2C, etc.
6 A. y: X: I2 f- s* ~5. High-quality verification with Code Coverage analysis and functional coverage analysis
! t9 q* d8 d$ G5 E6. Provide support to ATE/DFT and Validation

Job requirement:
1. Majoring in Electrical Engineering, microelectronics or image/graphics processing is preferred
8 _1 X3 p+ g# A' I# R" ?8 p9 z2. Master C/C++ coding and verilog coding, systemC and SystemVerilog is preferred
3. Strong DSP background is highly desirable
+ U. O( Z0 A! _6 y4. Knowledge of video coding standard including H264 MPEG-4 is preferable.
5. Knowledge of RTL design and verification
6. Knowledge of Perl and Tcl scripting
7. Able to understand Verilog RTL code, debug simulation errors, identify and fix RTL/Environment issues

Job requirement:
1. Majoring in Electrical Engineering, microelectronics or image/graphics processing is preferred
) R* @( [( B8 Q4 a; i5 I: u* L' u2. Master matlab is preferred
3. Master digital signal process
4. Master Runge-Kutta and math analysis
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9 J& Q: @  T; N联系人：
卢先生
; \3 C- D% D$ |' E: e( X请投简历至 邮箱：lush123@sina.com
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可以2500/月以上

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