Conexant 成都公司招聘

zl182005

Chengdu Conexant Regular Full-time positions:

2 B" V$ i) u, i: {* d  bSoC ASIC Design/Verification Engineer( Vacancy:1)
( B8 Q/ W+ L8 V/ Z% H) b
Job Responsibilities:
# {* T% B, M- E" m1. Integration of ARM processor/DSP co-processor and AMBA bus for SoC;
$ O' S) w9 i- D( F5 m& u  b2. Integration of H264 Codec , DDR, USB and PCIe etc for SoC;
; R* A% }4 b: h8 X/ k5 K6 a0 A! R3. Design erification of video surveillance and audio & voice processor with integrated CODEC and amplifier
4. Design SoC-level logic including clock, reset, and DFT;
5. Verification of AMBA-based DMA, Memory Subsystem, and all peripheral interfaces at unit level and SoC level
5 y) Q0 S7 d& @, V, \  @* |( n+ V6. Work with analog group and physical layout team on analog macro integration and synthesis/timing analysis.

! R; r+ h6 O5 O2 z5 L& {3 W1 ]Job Requirements:
1. 5+ years experience on SoC design and integration;
2. Hand-on experience in ASIC flow;
3. Experience of ARM/DSP/AMBA integration and/or verification;
4. Experience of DMA design and/or verification;
5. Experience of H264 Codec & DDR SoC integration and verification
6. Experience of video surveillance project design and verification
7. Experience of design erification for audio & voice processor with integrated Codec and amplifiers is a big plus
- K4 g) g' q. q% r& @; F2 W8. Domain knowledge on Nand Flash Controller, USB, and PCIe is a plus
" @6 ~0 P! J! D/ `0 h! e& [9. DFT (Memory BIST and scan) design background is a plus
" e! x2 f# T5 n4 t( }$ ~/ c4 D
ASIC Verification Engineer( Vacancy:2)

8 L, n2 g2 W; l# a- x2 sJob Description:
1. Instrumental in the development of infrastructure for the validation of OVM/UVM-based architectures and the verification of ASIC hardware.
2. Additional duties include the development of directed and random hardware verification environments, and the application of those environments to ASIC verification
8 G" N4 }) X! E! m) D. |3. Integration of VIP and functional verification agents in OVM/UVM verification environment to support coverage-driven verification
4. Understand and verify the functionality of a given design element within the context of the block, chip and overall system

1 {0 h% \" V" M& y; i+ P( O6 o9 i6 \Job Requirements:
& `& G' T/ f2 Q6 _1. Extensive Verilog experience with SOC verification environments.
% z' X9 U2 {+ Y* y  q2. Verification experience on digital signal processing for communication system.
# Q5 C/ u/ \- u, X$ Q! o3. Experience developing bus functional models, monitors, scoreboards, generators, functional coverage models
4. Experience with high level verification languages such as SystemC, SystemVerilog, OVM or VMM, Vera or Specman, and strong C++ programming background
5. Shell scripts and Tcl/Perl expertise, create runsim, lsf, regression management scripts
6. Able to understand Verilog RTL code, debug simulation errors, identify and fix RTL/Environment issues
+ P3 Z6 B* U& p2 C7. Strong DSP background is highly desirable
8. Experience on SD/HD/SDI video is a plus
9. H264 Codec design erification experienced is desired
& M& M  c! u+ _" O4 g: O- c10. Experience of design erification for cable equalizer is preferred

: B1 F0 s" o$ ?! ~/ R( XInter Algrithom Engineer( Vacancy:2)
) v# w. r) Y  k8 c4 K' VJob requirement:
6 g; H# S( t6 b0 s8 b1. Majoring in Electrical Engineering, microelectronics or image/graphics processing is preferred
( Q  |- C& J9 d. I; h. Z2. Master matlab is preferred
3. Master digital signal process or Opencv
4. Master and math analysis
& K! l, C! C3 w- g; R( k7 u

联系人：卢先生
0 y; H& p: o) }9 X& T请投简历至 邮箱：lush123@sina.com
& X* k2 \! f+ B

li3891419

<29><12>

罗格朗

支持！加油！